RISC-V is one of the most interesting architectures right now for hypervisor work — not because it's "ready", but because a lot of the stack is still being defined. Good news that RISC-V hypervisor spec is ratified and wont change anymore. Lets take a look on it together. If you're coming from x86 (KVM/VMX/SVM) or ARM (KVM/EL2), the mental model is familiar — but the details are much more fluid.
Bhyve (pronounced "bee hive") is a modern, lightweight Type-2 hypervisor and virtual machine manager primarily designed for FreeBSD, allowing users to run guest operating systems like Linux, Windows, and other BSDs.
At a high level, RISC-V virtualization is built around a privilege model extended to support hypervisors:
This is defined by the RISC-V Hypervisor Extension, often just called the H-extension.
If you've worked with bhyve before, HS-mode is effectively where virtual machine monitor lives, and VS-mode is your guest kernel context.
RISC-V uses a two-stage MMU model:
The hardware uses page table formats like:
On exception, guest traps into HS-mode, then hypervisor has to decide:
Virtualization adds a set of hypervisor CSRs:
These control:
RISC-V systems rely on the Supervisor Binary Interface, typically implemented by firmware like OpenSBI.
For virtualization, host kernel (HS) fully emulates SBI for the guest.