Running MDEPX on the STM32N6: Edge AI Meets Bare Metal
For years, embedded developers faced a hard ceiling: if your application needed serious neural network inference, you needed a microprocessor — with its Linux stack, boot times, and power budget. The STM32N6 demolishes that boundary. Released by STMicroelectronics in late 2024, it is the first STM32 to incorporate a fully custom, in-house neural processing unit: the Neural-ART Accelerator™.
This is not a bolted-on third-party NPU core. ST's teams began designing the Neural-ART architecture in 2016 — a nine-year investment that culminated in hardware capable of 600 GOPS at 1 GHz, delivering approximately 3 TOPS per watt. The result: a microcontroller that runs real-time person detection, keyword spotting, defect detection, and multi-class object recognition — while a conventional RTOS still orchestrates all surrounding tasks.
The key silicon specs tell the story. The CPU is an Arm Cortex-M55 running at 800 MHz — the first core to incorporate Arm Helium vector processing technology, bringing DSP-grade SIMD capabilities to the M-profile world. Around it sit 4.2 MB of contiguous embedded SRAM (the largest ever on an STM32), a NeoChrom™ GPU, an H.264 hardware encoder, a dedicated MIPI CSI-2 image signal processor pipeline, Gigabit Ethernet with TSN, hexa-SPI and OCTOSPI external memory interfaces, and a package range from 169 to 264 pins tolerant up to 125 °C.
Enter MDEPX: The Other Side of the Stack
While the STM32 ecosystem most commonly pairs with FreeRTOS, ThreadX (now Eclipse ThreadX), or bare-metal HAL code, a compelling alternative has been maturing for years in the open-source embedded world: MDEPX (also known as MDX or Machdep X), a BSD-licensed RTOS and bare-metal framework maintained Machine-Dependent Ltd.
MDEPX's architecture draws from FreeBSD kernel conventions, using FreeBSD's style(9) coding guide and BSD components like libc or libm (math) library. It supports ARMv7-M and ARMv8-M (the architecture family that includes Cortex-M55), MIPS32/64, RISC-V (rv32, rv64, SMP), and has shipped in production firmware for nRF9160 LTE-M devices, custom IoT hardware, and STM32MP2-adjacent designs. The STM32N6's Cortex-M55 implements ARMv8.1-M, squarely within MDEPX's supported territory.
Project Milestones
- Initial Hello World from SRAM
- Enable scheduler
- xSPI devices support (External PRAM, Octo Flash)
- Camera pipeline (MIPI CSI-2, DMIPP engine)
- Neural ART Inference enablement
- YOLOX models deployment
Conclusion
The STM32N6 is a genuine inflection point for embedded systems: a microcontroller that absorbs use-cases previously reserved for application processors, without sacrificing the determinism, low latency, and hardware simplicity that make microcontrollers compelling in the first place. It pairs that capability with the largest embedded RAM in the STM32 family and a peripheral set — Gigabit Ethernet, H.264, MIPI CSI-2 — that reads more like a multimedia SoC datasheet.
Running MDEPX on top of this hardware brings a clean, BSD-licensed, FreeBSD-convention RTOS that has already proven itself in production IoT designs. Its flat address space, SMP readiness, and native BSD libc make it a compelling alternative to the more mainstream RTOS options, especially for teams with a Unix/FreeBSD background or those who want a codebase they can fully audit and modify without commercial licensing friction.